AM29BDD160G datasheet(16/79 Pages) AMD

16 / 79 page

Am29BDD160G

June 7, 2006

read-while-program and read-while-erase current

specifications.

Simultaneous read/write operations are valid for both

the main Flash memory array and the SecSi OTP sec-

tor. Simultaneous operation is disabled during the CFI

and Password Program/Verify operations. PPB Pro-

gram/Erase operations and the Password Unlock op-

eration permit reading data from the large (75%) bank

while reading the operation status of these commands

from the small (25%) bank.

Table 3.

Top Boot Bank Select

Table 4.

Bottom Boot Bank Select

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V

IL, and OE# to VIH.

For program operations, in the x32-mode the device

accepts program data in 32-bit words and in the x16

mode the device accepts program data in 16-bit

words.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The

Sector Erase and Program Suspend Command sec-

tion has details on programming data to the device

using both standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 12 and 13 indicate

the address space that each sector occupies. A “sec-

tor address” consists of the address bits required to

uniquely select a sector. The “Command Definitions”

section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timing applies in

this mode. Refer to the “Autoselect Mode” section for

more information.

CC2 in the DC Characteristics table represents the ac-

tive current specification for erase or program modes.

The AC Characteristics section contains timing specifi-

cation tables and timing diagrams for erase or pro-

gram operations.

Accelerated Program and Erase Operations

The device offers accelerated program/erase opera-

tions through the ACC pin. When the system asserts

HH (12V) on the ACC pin, the device automatically

enters the Unlock Bypass mode. The system may

then write the two-cycle Unlock Bypass program com-

mand sequence to do accelerated programming. The

device uses the higher voltage on the ACC pin to ac-

celerate the operation. A sector that is being protected

with the WP# pin will still be protect during accelerated

program or Erase. Note that the ACC pin must not be

at V

HH during any operation other than accelerated

programming, or device damage may result.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Automatic Sleep Mode (ASM)

The automatic sleep mode minimizes Flash device en-

ergy consumption. While in asynchronous mode, the

device automatically enables this mode when ad-

dresses remain stable for t

ACC + 60 ns. The automatic

sleep mode is independent of the CE#, WE# and OE#

control signals. Standard address access timings pro-

vide new data when addresses are changed. While in

sleep mode, output data is latched and always avail-

able to the system. While in synchronous mode, the

device automatically enables this mode when either

the first active CLK level is greater than t

ACC or the

CLK runs slower than 5 MHz. Note that a new burst

operation is required to provide new data.

CC8 in the “DC Characteristics” section of page 53 rep-

resents the automatic sleep mode current specifica-

tion.

Standby Mode

When the system is not responding or writing to the

device, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# inputs are both held at Vcc

± 0.2 V.

The device requires standard access time (t

CE) for

read access, before it is ready to read data.

Bank

A18:A17

Bank 1

Bank 2

01, 1X

Bank

A18

Bank 1

0X, 10

Bank 2

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