AM29BDD160G datasheet(18/79 Pages) AMD

18 / 79 page

Am29BDD160G

June 7, 2006

Table 5.

Am29BDD160 Autoselect Codes (High Voltage Method)

L = Logic Low = V

IL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 18 and 20.

Asynchronous Read Operation

(Non-Burst)

The device has two control functions which must be

satisfied in order to obtain data at the outputs. CE# is

the power control and should be used for device selec-

tion. OE# is the output control and should be used to

gate data to the output pins if the device is selected.

The device is power-up in an asynchronous read

mode. In the asynchronous mode the device has two

control functions which must be satisfied in order to

obtain data at the outputs. CE# is the power control

and should be used for device selection. OE# is the

output control and should be used to gate data to the

output pins if the device is selected.

Address access time (t

ACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (t

CE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output

pins. The output enable access time is the delay from

the falling edge of OE# to valid data at the output pins

(assuming the addresses have been stable for at least

ACC–tOE time).

Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.

Figure 1.

Asynchronous Read Operation

Description

CE# OE# WE#

A18

A11 A10

DQ7

DQ0

Manufacturer ID:

AMD

VID

XXX

0001h

Read Cycle 1

VID

LLL

007Eh

Read Cycle 2

VID

0008h

Read Cycle 3

VID

0000h (top boot

block)

0001h (bottom boot

block)

PPB Protection

Status

SAX

VID

LLL

0000h (unprotected)

0001h (protected)

CE#

CLK

ADV#

A0-A18

DQ0-DQ31

OE#

WE#

IND/WAIT#

VIH

Float

VOH

Address 0

Address 1

Address 2

Address 3

Float

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