AM29BDD160G datasheet(39/79 Pages) AMD

39 / 79 page

June 7, 2006

Am29BDD160G

Unlock Bypass Reset Command

The Unlock Bypass Reset command places the device

in standard read/reset operating mode. Once exe-

cuted, normal read operations and user command se-

quences are available for execution.

The Unlock Bypass Program Command is ignored if

the SecSi sector is enabled.

Chip Erase Command

The Chip Erase command is used to erase the entire

flash memory contents of the chip by issuing a single

command. Chip erase is a six-bus cycle operation.

There are two “unlock” write cycles, followed by writing

the erase “set up” command. Two more “unlock” write

cycles are followed by the chip erase command. Chip

erase does not erase protected sectors.

The chip erase operation initiates the Embedded

Erase algorithm, which automatically preprograms and

verifies the entire memory to an all zero pattern prior

to electrical erase. The system is not required to pro-

vide any controls or timings during these operations.

Note that a hardware reset immediately terminates

the programming operation. The command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

The Embedded Erase algorithm erase begins on the

rising edge of the last WE# or CE# pulse (whichever

occurs first) in the command sequence. The status of

the erase operation is determined three ways:

■ Data# polling of the DQ7 pin (see DQ7: Data# Poll-

ing)

■ Checking the status of the toggle bit DQ6 (see DQ6:

Toggle Bit I)

■ Checking the status of the RY/BY# pin (see

RY/BY#: Ready/Busy#)

Once erasure has begun, only the Erase Suspend

command is valid. All other commands are ignored.

When the Embedded Erase algorithm is complete, the

device returns to reading array data, and addresses

are no longer latched. Note that an address change is

required to begin read valid array data.

Figure 5 illustrates the Embedded Erase Algorithm.

See the Erase/Program Operations tables in AC Char-

acteristics for parameters, and to Figure 22 for timing

diagrams.

Sector Erase Command

The Sector Erase command is used to erase individ-

ual sectors or the entire flash memory contents. Sec-

tor erase is a six-bus cycle operation. There are two

“unlock” write cycles, followed by writing the erase “set

up” command. Two more “unlock” write cycles are

then followed by the erase command (30h). The sec-

tor address (any address location within the desired

sector) is latched on the falling edge of WE# or CE#

(whichever occurs last) while the command (30h) is

latched on the rising edge of WE# or CE# (whichever

occurs first).

Specifying multiple sectors for erase is accomplished

by writing the six bus cycle operation, as described

above, and then following it by additional writes of only

the last cycle of the Sector Erase command to ad-

dresses or other sectors to be erased. The time be-

tween Sector Erase command writes must be less

than 80 µs, otherwise the command is rejected. It is

recommended that processor interrupts be disabled

during this time to guarantee this critical timing condi-

tion. The interrupts can be re-enabled after the last

Sector Erase command is written. A time-out of 80 µs

from the rising edge of the last WE# (or CE#) will ini-

tiate the execution of the Sector Erase command(s). If

another falling edge of the WE# (or CE#) occurs within

the 80 µs time-out window, the timer is reset. Once the

80 µs window has timed out and erasure has begun,

only the Erase Suspend command is recognized (see

Sector Erase and Program Suspend Command and

Sector Erase and Program Resume Command sec-

tions). If that occurs, the sector erase command se-

quence should be reinitiated once that bank has

returned to reading array data, to ensure data integrity.

Loading the sector erase registers may be done in any

sequence and with any number of sectors.

Sector erase does not require the user to program the

device prior to erase. The device automatically prepro-

grams all memory locations, within sectors to be

erased, prior to electrical erase. When erasing a sec-

tor or sectors, the remaining unselected sectors or the

write protected sectors are unaffected. The system is

not required to provide any controls or timings during

sector erase operations. The Erase Suspend and

Erase Resume commands may be written as often as

required during a sector erase operation.

Automatic sector erase operations begin on the rising

edge of the WE# or CE# pulse of the last sector erase

command issued, and once the 80 µs time-out window

has expired. The status of the sector erase operation

is determined three ways:

■ Data# polling of the DQ7 pin

■ Checking the status of the toggle bit DQ6

■ Checking the status of the RY/BY# pin

Further status of device activity during the sector

erase operation is determined using toggle bit DQ2

(refer to DQ2: Toggle Bit II).

When the Embedded Erase algorithm is complete, the

device returns to reading array data, and addresses

are no longer latched. Note that an address change is

required to begin read valid array data.

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