AM29BDD160G datasheet(19/79 Pages) AMD

19 / 79 page

June 7, 2006

Am29BDD160G

Synchronous (Burst) Read Operation

The Am29BDD160 is capable of performing burst read

operations to improve total system data throughput.

The device is available in three burst modes of opera-

tion: linear and burst mode. 2, 4 and 8 double word

(x32) and 4 and 8 word (x16) accesses are config-

urable as either sequential burst accesses. 16 and 32

word (x16) accesses are only configurable as linear

burst accesses. Additional options for all burst modes

include initial access delay configurations (2–16

CLKs) Device configuration for burst mode operation

is accomplished by writing the Configuration Register

with the desired burst configuration information. Once

the Configuration Register is written to enable burst

mode operation, all subsequent reads from the array

are returned using the burst mode protocols. Like the

main memory access, the SecSi Sector memory is ac-

cessed with the same burst or asynchronous timing as

defined in the Configuration Register. However, the

user must recognize that continuous burst operations

past the 256 byte SecSi boundary returns invalid data.

Burst read operations occur only to the main flash

memory arrays. The Configuration Register and pro-

tection bits are treated as single cycle reads, even

when burst mode is enabled. Read operations to

these locations results in the data remaining valid

while OE# is at V

IL, regardless of the number of CLK

cycles applied to the device.

Linear Burst Read Operations

Linear burst read mode reads either 4, 8, 16, or 32

words (1 word = 16 bits), depending upon the Configu-

ration Register option. If the device is configured with

a 32 bit interface (WORD# = V

IH), the burst access is

comprised of 4 clocked reads for 8 words and 16

clocked reads for 32 words (See Table 6 for all valid

burst output sequences). The number of clocked

reads is doubled when the device is configured in the

16-bit data bus mode (WORD# = V

IL). The IND/WAIT#

pin transitions active (V

IL) during the last transfer of

data during a linear burst read before a wrap around,

indicating that the system should initiate another

ADV# to start the next burst access. If the system con-

tinues to clock the device, the next access wraps

around to the starting address of the previous burst

access. The IND/WAIT# signal remains inactive (float-

ing) when not active. See Table 6 for a complete 32

and 16 bit data bus interface order. 16 and 32 word

options are restricted to sequential burst accesses,

only.

Table 6.

16-Bit and 32-Bit Linear and BurstData Order

Data Transfer Sequence

(Independent of the WORD#

pin)

Output Data Sequence (Initial Access Address)

(x16)

Two Linear Data Transfers,

(x32 only)

0-1 (A0 = 0)

1-0 (A0 = 1)

Four Linear Data Transfers

0-1-2-3 (A0:A-1/A1-A0 = 00)

1-2-3-0 (A0:A-1/A1-A0 = 01)

2-3-0-1 (A:A-1/A1-A0 = 10)

3-0-1-2 (A0:A-1/A1-A0 = 11)

Eight Linear Data Transfers

0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)

1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)

2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)

3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)

4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)

5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)

6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)

7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)

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