AM29BDS640G datasheet(18/77 Pages) AMD

18 / 77 page

Am29BDS640G

25903C2 May 9, 2006

Data

Sheet

cycle program command sequence as required by the Unlock Bypass mode. Re-

moving VID from the ACC input returns the device to normal operation. Note that

sectors must be unlocked prior to raising ACC to VID. Note that the ACC pin must

not be at VID for operations other than accelerated programming, or device dam-

age may result. In addition, the ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

mode may only be entered and used when in the asynchronous read mode. Refer

to the “Autoselect Command Sequence” section on page 31 section for more

information.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CMOS standby mode when the CE# and RESET# inputs are

both held at VCC ± 0.2 V. The device requires standard access time (tCE) for read

access, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

ICC3 in the DC Characteristics table represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. While in

asynchronous mode, the device automatically enables this mode when addresses

remain stable for tACC + 60 ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address access timings provide

new data when addresses are changed. While in sleep mode, output data is

latched and always available to the system. While in synchronous mode, the de-

vice automatically enables this mode when either the first active CLK edge occurs

after tACC or the CLK runs slower than 5MHz. Note that a new burst operation is

required to provide new data.

ICC4 in the “DC Characteristics” section on page 45 represents the automatic

sleep mode current specification.

RESET#: Hardware Reset Input

The RESET# input provides a hardware method of resetting the device to reading

array data. When RESET# is driven low for at least a period of tRP, the device im-

mediately terminates any operation in progress, tristates all outputs, resets the

configuration register, and ignores all read/write commands for the duration of

the RESET# pulse. The device also resets the internal state machine to reading

array data. The operation that was interrupted should be reinitiated once the de-

vice is ready to accept another command sequence, to ensure data integrity.

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