AM29BDS640G datasheet(36/77 Pages) AMD

36 / 77 page

Am29BDS640G

25903C2 May 9, 2006

Data

Sheet

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm auto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these operations. Table 13, “Command Definitions,” on page 37

shows the address and data requirements for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read

mode and addresses are no longer latched. The system can determine the status

of the erase operation by using DQ7 or DQ6/DQ2. Refer to the “Write Operation

Status” section for information on these status bits.

Any commands written during the chip erase operation are ignored. However,

note that a hardware reset immediately terminates the erase operation. If that

occurs, the chip erase command sequence should be reinitiated once that bank

has returned to reading array data, to ensure data integrity.

The host system may also initiate the chip erase command sequence while the

device is in the unlock bypass mode. The command sequence is two cycles in

length instead of six cycles. See Table 13 for details on the unlock bypass com-

mand sequences.

Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Pro-

gram Operations table in the AC Characteristics section for parameters and timing

diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Table 13 shows the address

and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Em-

bedded Erase algorithm automatically programs and verifies the entire memory

for an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of no less than

35 µs occurs. During the time-out period, additional sector addresses and sector

erase commands may be written. Loading the sector erase buffer may be done

in any sequence, and the number of sectors may be from one sector to all sectors.

The time between these additional cycles must be less than 50 µs, otherwise era-

sure may begin. Any sector erase address and command following the exceeded

time-out may or may not be accepted. It is recommended that processor inter-

rupts be disabled during this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase command is written. Any

command other than Sector Erase or Erase Suspend during the time-out period

resets that bank to the read mode. The system must rewrite the command se-

quence and any additional addresses and commands.

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