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AM29BDS640G 데이터시트(PDF) 50 Page - Advanced Micro Devices

부품명 AM29BDS640G
상세설명  64 Megabit (4 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PDF  77 Pages
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제조업체  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29BDS640G 데이터시트(HTML) 50 Page - Advanced Micro Devices

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Am29BDS640G
25903C2 May 9, 2006
Data
Sheet
AC Characteristics
Synchronous/Burst Read
Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
Parameter
Description
98
(40 MHz)
78
(54 MHz)
93
(40 MHz)
73
(54 MHz) Unit
JEDEC Standard
tIACC
Latency (Even Address in Handshake
Mode)
Max
9587.595
88
ns
Parameter
Description
98, 99
(40 MHz)
78, 79
(54 MHz)
93, 94
(40 MHz)
73, 74
(54 MHz) Unit
JEDEC Standard
tIACC
Latency—(Non-Handshake or Odd
Address in Handshake mode)
Max
120
106
120
106.5
ns
tBACC
Burst Access Time Valid Clock to
Output Delay
Max
2013.520
14
ns
tACS
Address Setup Time to CLK (See Note)
Min
5
ns
tACH
Address Hold Time from CLK (See
Note)
Min
7
ns
tBDH
Data Hold Time from Next Clock Cycle
Max
4
ns
tOE
Output Enable to Output Valid
Max
20
13.5
20
14
ns
tCEZ
Chip Enable to High Z
Max
10
10.5
10.5
ns
tOEZ
Output Enable to High Z
Max
10
10.5
10.5
ns
tCES
CE# Setup Time to CLK
Min
5
ns
tRDYS
RDY Setup Time to CLK
Min
5
4.5
4.5
ns
tRACC
Ready Access Time from CLK
Max
20
13.5
20
14
ns
tAAS
Address Setup Time to AVD# (See
Note)
Min
5
ns
tAAH
Address Hold Time to AVD# (See Note)
Min
7
ns
tCAS
CE# Setup Time to AVD#
Min
0
ns
tAVC
AVD# Low to CLK
Min
5
ns
tAVD
AVD# Pulse
Min
12
ns
tACC
Access Time
Max
70
ns



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