IMX7DCEC datasheet(30/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

The NVCC_DRAM_CKE can be still ON during SNVS/LPSR mode to keep the CKE/RESET pad in

correct state to hold DRAM device in self-refresh mode.

The NVCC_XXX can be off in RUN mode / Low Power mode if all the pads in that IO bank is not used

in the application, the NVCC_XXX supply could be tied to GND.

The VDD_USB_OTG1_3P3_IN and VDD_USB_OTG2_3P3_IN are fully asynchronous to other power

rails, so it can be either ON/OFF in any of the power modes.

4.1.6.1

OFF Mode

In OFF mode, all the power rails are shut off.

4.1.6.2

SNVS Mode

SNVS mode is also called RTC mode, where only the power for the SNVS domain remain on. In this

mode, only the RTC and tamper detection logic is still active.

The power consumption in SNVS model with all the tamper detection logic enabled will be less than

5 uA @ 3.0 V on VDD_SNVS_IN for typical silicon at 25C.

The external DRAM device can keep in self-refresh when the chip stays in SNVS mode with

NVCC_DRAM_CKE still powered. During the state transition between SNVS mode to/from ON mode,

the DRAM_CKE pad and DRAM_RESET pad has to always stay in correct state to keep DRAM in

self-refresh mode. No glitch / floating is allowed.

4.1.6.3

LPSR Mode

LPSR is considered as an extension of the SNVS mode. All the features supported in SNVS mode is also

supported in LPSR mode, including the capability of keeping DRAM device in self-refresh.

In LPSR mode, three additional power rails will remain on: VDD_LPSR_IN, NVCC_GPIO1, and

NVCC_GPIO2. These three power rails are used to supply the logic and IO pads in the LPSR domain. The

purpose of this mode is to retain the state of 16 GPIO pads, so the other components in the whole system

will have their control signal in correct state.

Among all the 16 GPIO pads, the NVCC_GPIO1 supply the power for 8 GPIO pads, and the

NVCC_GPIO2 supply the power for the other 8 GPIO pads. This allows the SoC to have some of its GPIO

working at 1.8 V while others working at 3.3 V in the LPSR mode.

NVCC_DRAM_CKE

OFF

OFF / ON

NVCC_XXX

OFF

ON / OFF

VDD_USB_OTG1_3P3_IN

VDD_USB_OTG2_3P3_IN

OFF / ON

ON / OFF

Table 14. Power modes(continued)

Power rail

OFF

SVNS

LPSR

RUN

Low Power

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