IMX7DCEC datasheet(121/161 Pages) NXP

121 / 161 page

Boot mode configuration

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

121

SPI

ECSPI-2

ECSPI2_SCLK, ECSPI2_MOSI, ECSPI2_MISO,

ECSPI2_SS0, ENET1_RX_CTL, ENET1_RXC,

ENET1_TD0

The chip-select pin used depends

on the fuse "CS select (SPI only)"

SPI

ECSPI-3

SAI2_TXFS, SAI2_TXC, SAI2_RXD, SAI2_TXD,

SD1_DATA3, SD2_CD_B, SD2_WP

The chip-select pin used depends

on the fuse "CS select (SPI only)"

SPI

ECSPI-4

SD1_CD_B, SD1_WP, SD1_RESET_B, SD1_CLK,

SD1_CMD, SD1_DATA0, SD1_DATA1

The chip-select pin used depends

on the fuse "CS select (SPI only)"

EIM

EPDC_SDCE2, EPDC_SDCE3, EPDC_GDCLK,

EPDC_GDOE, EPDC_GDRL, EPDC_GDSP,

EPDC_BDR0, LCD_DAT20, LCD_DAT21, LCD_DAT22,

LCD_DAT23, EPDC_D8, EPDC_D9, EPDC_D10,

EPDC_D12, EPDC_D14, EPDC_PWRSTAT

Used for NOR, OneNAND boot

Only CS0 is supported. Allocated

pads may differ depending on mux

mode. See the “System Boot,

Fusemap, and eFuse” chapter of

the i.MX 7Dual Application

Processor Reference Manual

(IMX7DRM) for details.

NAND Flash

GPMI

SD3_CLK, SD3_CMD, SD3_DATA0, SD3_DATA1,

SD3_DATA2, SD3_DATA3, SD3_DATA4, SD3_DATA5,

SD3_DATA6, SD3_DATA7, SD3_STROBE,

SD3_RESET_B, SAI1_TXC, SAI1_TXFS, SAI1_TXD

8 bit

Only CS0 is supported

SD/MMC

USDHC-1

SD1_CD_B, SD1_RESET_B, SD1_CLK, SD1_CMD,

SD1_DATA0, SD1_DATA1, SD1_DATA2, SD1_DATA3,

GPIO1_IO08, ECSPI2_SCLK, ECSPI2_MOSI,

ECSPI2_MISO, ECSPI2_SS0

1, 4, or 8 bit

SD/MMC

USDHC-2

SD2_RESET_B, SD2_CLK, SD2_CMD, SD2_DATA0,

SD2_DATA1, SD2_DATA2, SD2_DATA3, GPIO1_IO12,

ECSPI1_SCLK, ECSPI1_MOSI, ECSPI1_MISO,

ECSPI1_SS0

1, 4, or 8 bit

SD/MMC

USDHC-3

SD3_CLK, SD3_CMD, SD3_DAT0, SD3_DAT1,

SD3_DAT2, SD3_DAT3, SD3_DAT4, SD3_DAT5,

SD3_DAT6, SD3_DAT7, SD3_RESET_B

1, 4, or 8 bit

USB

USB-OTG

PHY

—

Table 97. Interface allocation during boot(continued)

Interface

IP Instance

Allocated Pads During Boot

Comment

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