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CONTROL INTERFACE TIMING REQUIREMENTS (PCM1850A)

1.4 V

MS

LSB

1.4 V

1.4 V

MC

MD

T0013-06

Slave Address

Packet Protocol

PCM1850A

PCM1851A

SLES173 – MARCH 2006

Figure 29 shows a detailed timing diagram for the serial control interface of the PCM1850A. These timing

parameters are critical for proper control port operation.

SYMBOL

PARAMETER

MIN

MAX

UNIT

MC pulse cycle time

100

ns

MC LOW-level time

40

ns

MC HIGH-level time

40

ns

MS HIGH-level time

80

ns

MS falling edge to MC rising edge

15

ns

15

ns

MD hold time

15

ns

MD setup time

15

ns

(1)

MC rising edge for LSB to MS rising edge

Figure 29. PCM1850A Control Interface Timing

MSB

LSB

1

0

0

1

0

1

ADR

R/nW

The PCM1851A has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory

preset to 100101. The last bit of the address byte is the device select bit, which can be user-defined by the ADR

pin (pin 30). A maximum of two PCM1851As can be connected on the same bus at one time. Each PCM1851A

responds when it receives its own slave address.

A master device must control packet protocol, which consists of start condition, slave address with read/write bit,

data if write or acknowledgement if read, and stop condition. The PCM1851A supports only slave receivers, so

the R/W bit must be set to 0.

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