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PCM1850APJTG4 데이터시트(PDF) 26 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
부품명 PCM1850APJTG4
상세설명  24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 쨈 2-CHANNEL MUX AND PGAE
PDF  32 Pages
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제조업체  BURR-BROWN [Burr-Brown (TI)]
홈페이지  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

PCM1850APJTG4 데이터시트(HTML) 26 Page - Burr-Brown (TI)

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TIMING DIAGRAM
SDA
SCL
t(BUF)
t(D-SU)
t(D-HD)
Start
t(LOW)
t(S-HD)
t(SCL-F)
t(SCL-R)
t(HI)
Repeated Start
t(RS-SU)
t(RS-HD)
t(SDA-F)
t(SDA-R)
t(P-SU)
Stop
T0050-01
PCM1850A
PCM1851A
SLES173 – MARCH 2006
SYMBOL
PARAMETER
MIN
MAX
UNIT
f(SCL)
SCL clock frequency
100
kHz
t(BUF)
Bus free time between STOP and START conditions
4.7
µs
t(LOW)
Low period of the SCL clock
4.7
µs
t(HI)
High period of the SCL clock
4
µs
t(RS-SU)
Setup time for START/repeated START condition
4.7
µs
t(S-HD), t(RS-HD)
Hold time for START/repeated START condition
4
µs
t(D-SU)
Data setup time
250
ns
t(D-HD)
Data hold time
0
900
ns
t(SCL-R)
Rise time of SCL signal
20 + 0.1 CB
1000
ns
t(SCL-F)
Fall time of SCL signal
20 + 0.1 CB
1000
ns
t(SDA-R)
Rise time of SDA signal
20 + 0.1 CB
1000
ns
t(SDA-F)
Fall time of SDA signal
20 + 0.1 CB
1000
ns
t(P-SU)
Setup time for STOP condition
4
µs
CB
Capacitive load for SDA and SCL lines
400
pF
VNH
Noise margin at HIGH level for each connected device (including hysteresis)
0.2 VDD
V
Figure 32. PCM1851A Control Interface Timing Requirements
26
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