PCM1850APJTG4 datasheet(14/32 Pages) BURR-BROWN

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DETAILED DESCRIPTION

SYSTEM CLOCK

t(SCKH)

SCKI

t(SCKL)

2 V

0.8 V

T0005-11

PCM1850A

PCM1851A

SLES173 – MARCH 2006

The PCM1850A/1851A supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio

sampling frequency. The system clock must be supplied on SCKI (pin 7).

The PCM1850A/1851A has a system clock detection circuit which automatically senses if the system clock is

operating at 256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be

selected by mode control via the serial port. The 768-fS system clock is not available in master mode or for fS =

88.2 kHz and 96 kHz in the slave mode. The system clock is divided into 128 fS and 64 fS automatically, and

these frequencies are used to operate the digital filter and the delta-sigma modulator, respectively.

Table 1 shows the relationship of typical sampling frequency to system clock frequency, and Figure 20 shows

system clock timing.

Table 1. Sampling Frequency and System Clock Frequency

SYSTEM CLOCK FREQUENCY (MHz)

SAMPLING RATE FREQUENCY

(kHz)

256 fS

384 fS

512 fS

768 fS(1)

8.192

12.288

16.384

24.576

44.1

11.2896

16.9344

22.5792

33.8688

12.288

18.432

24.576

36.864

16.384

24.576

32.768

49.152

88.2

22.5792

33.8688

45.1584

—

24.576

36.864

49.152

—

(1)

Slave mode only

SYMBOL

PARAMETER

MIN

MAX

UNIT

t(SCKH)

System clock pulse duration, HIGH

t(SCKL)

System clock pulse duration, LOW

Figure 20. System Clock Timing

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