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VT8235 데이터시트(PDF) 67 Page - VIA Technologies, Inc. |
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VT8235 데이터시트(HTML) 67 Page - VIA Technologies, Inc. |
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67 / 145 page ![]() VT8235 V-Link South Bridge Revision 1.22 October 24, 2002 -61- Device 17 Function 0 Bus Control Registers UrpuytvrÃDp XrÃ8rp Device 17 Function 0 Registers – Bus Control and Power Management All registers are located in the device 17 function 0 configuration space of the VT8235. These registers are accessed through PCI configuration mechanism #1 via I/O address 0CF8h / 0CFCh. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h)......................................... RO Offset 3-2 - Device ID (3177h) .......................................... RO Offset 5-4 - Command.......................................................RW 15-8 Reserved ........................................ always reads 0 7 Address / Data Stepping 0 Disable 1 Enable ................................................... default 6-4 Reserved ........................................ always reads 0 3 Special Cycle Enable .......................RW, default = 0 2 Bus Master ........................................ always reads 1 1 Memory Space .................................... RO, reads as 1 0 I/O Space ........................................ RO, reads as 1 Offset 7-6 - Status ...........................................................RWC 15 Detected Parity Error ....................write one to clear 14 Signalled System Error ...................... always reads 0 13 Signalled Master Abort .................write one to clear 12 Received Target Abort ...................write one to clear 11 Signalled Target Abort ..................write one to clear 10-9 DEVSEL# Timing .................... fixed at 01 (medium) 8 Data Parity Detected Reads 1 if PERR# is asserted (driven or observed) or a bus master data parity error occurred. 7 Fast Back-to-Back Capable ............... always reads 0 6-0 Reserved ........................................ always reads 0 Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Revision ID Offset 9 - Program Interface (00h) ................................... RO Offset A - Sub Class Code (01h) ....................................... RO Offset B - Class Code (06h) ............................................... RO Offset E - Header Type (80h)............................................ RO 7-0 Header Type Code......... 80h (Multifunction Device) Offset F - BIST (00h) ......................................................... RO Offset 2F-2C - Subsystem ID ............................................ RO Use offset 70-73 to change the value returned. |
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