VT8235 datasheet(72/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-66-

Device 17 Function 0 Bus Control Registers

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Serial IRQ, LPC, and PC/PCI DMA Control

Offset 52 – Serial IRQ & LPC Control (00h)..................RW

Reserved

........................................ always reads 0

LPC Short Wait Abort

Disable .................................................. default

Enable.

During a short wait, the cycle is

aborted after 8Ts.

LPC Frame Wait State Time

Frame Wait State is 1T.......................... default

Frame Wait State is 2T

LPC Stop to Start Frame Wait State

Enable.

One idle state is inserted between

Stop and Start ........................................ default

Disable.

Stop is followed immediately by

Start.

Serial IRQ

Disable .................................................. default

Enable (IRQ asserted via SerialIRQ pin AE10)

Serial IRQ Quiet Mode

Continuous Mode .................................. default

Quiet Mode

1-0

Serial IRQ Start-Frame Width

00 4 PCI Clocks ......................................... default

01 6 PCI Clocks

10 8 PCI Clocks

11 10 PCI Clocks

Offset 53 – PC/PCI DMA Control ...................................RW

PCI DMA Pair A and Pair B

Disable .................................................. default

Enable

PCI DMA Channel 7

Disable .................................................. default

Enable

PCI DMA Channel 6

Disable .................................................. default

Enable

PCI DMA Channel 5

Disable .................................................. default

Enable

PCI DMA Channel 3

Disable .................................................. default

Enable

PCI DMA Channel 2

Disable .................................................. default

Enable

PCI DMA Channel 1

Disable .................................................. default

Enable

PCI DMA Channel 0

Disable .................................................. default

Enable

Plug and Play Control - PCI

Offset 54 - PCI Interrupt Polarity................................... RW

7-4

Reserved

........................................always reads 0

The following bits all default to “level” triggered (0)

PCI INTA# Invert (edge) / Non-invert (level)

. (1/0)

PCI INTB# Invert (edge) / Non-invert (level)

. (1/0)

PCI INTC# Invert (edge) / Non-invert (level)

. (1/0)

PCI INTD# Invert (edge) / Non-invert (level)

. (1/0)

Note:

PCI INTA-D# normally connect to PCI interrupt pins

INTA-D# (see pin definitions for more information).

Offset 55 – PCI PNP Interrupt Routing 1 ...................... RW

7-4

PCI INTA# Routing

(see PnP IRQ routing table)

3-0

Reserved

........................................always reads 0

Offset 56 – PCI PNP Interrupt Routing 2 ...................... RW

7-4

PCI INTC# Routing

(see PnP IRQ routing table)

3-0

PCI INTB# Routing

(see PnP IRQ routing table)

Offset 57 – PCI PNP Interrupt Routing 3 ...................... RW

7-4

PCI INTD# Routing

(see PnP IRQ routing table)

3-0 Reserved

........................................always reads 0

Table 11. PnP IRQ Routing Table

0000 Disabled ................................................. default

0001 IRQ1

0010 Reserved

0011 IRQ3

0100 IRQ4

0101 IRQ5

0110 IRQ6

0111 IRQ7

1000 Reserved

1001 IRQ9

1010 IRQ10

1011 IRQ11

1100 IRQ12

1101 Reserved

1110 IRQ14

1111 IRQ15

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