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CLRC663 데이터시트(PDF) 64 Page - NXP Semiconductors |
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CLRC663 데이터시트(HTML) 64 Page - NXP Semiconductors |
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64 / 177 page ![]() NXP Semiconductors CLRC663 High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus Bit Symbol Description 7 RegEn If this bit is set to logic 1, the register HostCtrl_reg can be changed at the next register access. The next write access clears this bit automatically. 6 BusHost Set to logic 1, the bus is controlled by the host. This bit cannot be set together with the bit BusSAM. This bit can only be set if the bit RegEn is previously set. 5 BusSAM Set to logic 1, the bus is controlled by the SAM. This bit cannot be set together with Bus Host. This bit can only be set if the bit RegEn is previously set. 4 RFU - 3 to 2 SAMInterface 0h:SAM Interface switched off 1h:SAM Interface SPI active 2h:SAM Interface I2CL active 3h:SAM Interface I2C active 1 to 0 RFU - Table 54. HostCtrl bits 9.4 FIFO configuration register 9.4.1 FIFOControl FIFOControl defines the characteristics of the FIFO Bit 7 6 5 4 3 2 1 0 Symbol FIFOSize HiAlert LoAlert FIFOFlush RFU Water LevelExtBit FIFOLengthExtBits Access rights r/w r r w - r/w r Table 55. FIFOControl register (address 02h); Bit Symbol Description 7 FIFOSize Set to logic 1, FIFO size is 255 bytes; Set to logic 0, FIFO size is 512 bytes. It is recommended to change the FIFO size only, when the FIFO content had been cleared. 6 HiAlert Set to logic 1, when the number of bytes stored in the FIFO buffer fulfils the following equation: HiAlert = (FIFOSize - FIFOLength) <= WaterLevel 5 LoAlert Set to logic 1, when the number of bytes stored in the FIFO buffer fulfils the following conditions: LoAlert =1 if FIFOLength <= WaterLevel 4 FIFOFlush Set to logic 1 clears the FIFO buffer. Reading this bit will always return 0 3 RFU - 2 WaterLevelExtBit Defines the bit 8 (MSB) for the waterlevel (extension of register WaterLevel). This bit is only evaluated in the 512-byte FIFO mode. Bits 7..0 are defined in register Water Level. Table 56. FIFOControl bits CLRC663 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5.3 — 3 January 2024 64 / 177 |
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