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CLRC663 데이터시트(PDF) 67 Page - NXP Semiconductors

부품명 CLRC663
상세설명  High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
PDF  177 Pages
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제조업체  NXP [NXP Semiconductors]
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NXP Semiconductors
CLRC663
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Bit
Symbol
Description
5
LoAlertIRQ
Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert, LoAlertIRQ stores this
event.
4
IdleIRQ
Set, when a command terminates by itself e.g. when the Command changes its value from any
command to the Idle command. If an unknown command is started, the Command changes its
content to the idle state and the bit IdleIRQ is set. Starting the Idle command by the Controller
does not set bit IdleIRQ.
3
TxIRQ
Set, when data transmission is completed, which is immediately after the last bit is sent.
2
RxIRQ
Set, when the receiver detects the end of a data stream.
Note: This flag is no indication that the received data stream is correct. The error flags have to
be evaluated to get the status of the reception.
1
ErrIRQ
Set, when the one of the following errors is set:
FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr.
0
RxSOFlrq
Set, when a SOF or a subcarrier is detected.
Table 64. IRQ0 bits...continued
9.5.2 IRQ1 register
Interrupt request register 1.
Bit
7
6
5
4
3
2
1
0
Symbol
Set
GlobalIRQ LPCD_IRQ Timer4IRQ
Timer3IRQ
Timer2IRQ
Timer1IRQ Timer0IRQ
Access
rights
w
dy
dy
dy
dy
dy
dy
dy
Table 65. IRQ1 register (address 07h)
Bit
Symbol
Description
7
Set
1: writing a 1 to a bit position 5..0 sets the interrupt request
0: Writing a 1 to a bit position 5..0 clears the interrupt request
6
GlobalIRQ
Set, if an enabled IRQ occurs.
5
LPCD_IRQ
Set if a card is detected in Low-power card detection sequence.
4
Timer4IRQ
Set to logic 1 when Timer4 has an underflow.
3
Timer3IRQ
Set to logic 1 when Timer3 has an underflow.
2
Timer2IRQ
Set to logic 1 when Timer2 has an underflow.
1
Timer1IRQ
Set to logic 1 when Timer1 has an underflow.
0
Timer0IRQ
Set to logic 1 when Timer0 has an underflow.
Table 66. IRQ1 bits
9.5.3 IRQ0En register
Interrupt request enable register for IRQ0. This register allows defining if an interrupt request is processed by
the CLRC663.
CLRC663
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.3 — 3 January 2024
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