TSL2521 datasheet(33/81 Pages) OSRAM

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Page 32

Datasheet, Public

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[v3-00] 2022-Dec-21

TSL2521 − Register O ver view

STATUS3 Register

Figure 37:

STATUS3

Note(s):

1. Return to the Register Map (0x9E).

Addr: 0x9E

STATUS3

Bit

Field

Reset

Type

Bit Description

AINT_HYST_

STATE_VALID

Indicates that the ALS interrupt hysteresis state

AINT_HYST_STATE is valid. It will get asserted as

soon as the value exceeds the high or the low ALS

interrupt thresholds by APERS times. It is

automatically cleared with AEN or PON set to 0.

AINT_HYST_

STATE_RD

This bit indicates the state in the hysteresis defined

with AINT_AILT and AINT_AIHT, Preset of state is

possible before AEN is set. The contents of this

case of AINT interrupt direct mode.

5AINT_AIHT

R/W

ALS Interrupt High. Indicates that an ALS interrupt

occurred because the ALS data exceeded the high

threshold. Writing ‘1’ to this bit clears this interrupt.

4AINT_AILT

R/W

ALS Interrupt Low. Indicates that an ALS interrupt

occurred because the ALS data is below the low

threshold. Writing ‘1’ to this bit clears this interrupt.

VSYNC_LOST

Indicates that synchronization is out of sync with

clock provided at vsync pin. Default value is “1”

since device always starts unsynchronized. The

detected vsync clock is not within the expected

range. Please see VSYNC_PERIOD_TARGET for more

details.

2Reserved

OSC_CALIB_

SATURATION

Indicates that oscillator calibration with the current

values of TRIM_OSC and OSC_TUNE is out of range

abs(TRIM_OSC+OSC_TUNE) > 32

OSC_CALIB_

FINISHED

Indicates that oscillator calibration is finished.

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