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S12SCIV2/D 데이터시트(PDF) 109 Page - Freescale Semiconductor, Inc |
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S12SCIV2/D 데이터시트(HTML) 109 Page - Freescale Semiconductor, Inc |
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109 / 130 page ![]() MC9S12H256 Device User Guide — V01.18 A.4.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.4.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Figure A-2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-15. The VCO Gain at the desired VCO output frequency is approximated by: The phase detector relationship is given by: ich is the current in tracking mode. 3. XCLKS =1 during reset fosc 1 refdv+1 fref Phase Detector VCO KV 1 synr+1 fvco Loop Divider KΦ 1 2 ∆ fcmp Cs R Cp VDDPLL K V K 1 e f 1 f vco – () K 1 1V ⋅ ----------------------- ⋅ = KΦ i ch KV ⋅ = Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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