DSP56362P datasheet(45/152 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

3-19

Figure 3-13 DRAM Page Mode Wait States Selection Guide

Table 3-9

DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3

No.

Characteristics

Symbol

Expression

20 MHz4

30 MHz

Unit

Min

Max

Min

Max

131 Page mode cycle time for two consecutive

accesses of the same direction

Page mode cycle time for mixed (read and write)

accesses.

tPC

× T

1.25 x Tc

100.0

62.5

—

66.7

41.7

—

132 CAS assertion to data valid (read)

tCAC

TC − 7.5

—

42.5

—

25.8

133 Column address valid to data valid (read)

tAA

1.5

× T

C − 7.5

—

67.5

—

42.5

134 CAS deassertion to data not valid (read hold

time)

tOFF

0.0

—

0.0

—

135 Last CAS assertion to RAS deassertion

tRSH

0.75

× T

C − 4.0

33.5

—

21.0

—

136 Previous CAS deassertion to RAS deassertion

tRHCP

× T

C − 4.0

96.0

—

62.7

—

Chip Frequency

(MHz)

DRAM Type

(tRAC ns)

100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

Note: This figure should be used for primary selection. For

exact and detailed timings see the following tables.

AA0472

120

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