DSP56362P datasheet(48/152 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56362 Technical Data, Rev. 4

3-22

Freescale Semiconductor

153

RD assertion to data valid

tGA

1.75

× T

C − 6.5

—

15.4

154

RD deassertion to data not valid7

tGZ

0.0

—

155

WR assertion to data active

0.75

× T

C − 0.3

9.1

—

156

WR deassertion to data high impedance

0.25

× T

—3.1

1 The number of wait states for Page mode access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 The asynchronous delays specified in the expressions are valid for DSP56362.

4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t

PC equals 3 × TC for

read-after-read or write-after-write sequences).

5 There are not any fast enough DRAMs to fit to two wait states Page mode @ 100MHz. See

Figure 3-13.

6 BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

7 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

Table 3-11

DRAM Page Mode Timings, Three Wait States1, 2, 3, 4

No.

Characteristics

Symbol

Expression

100 MHz

Unit

Min

Max

131 Page mode cycle time for two consecutive accesses of the

same direction

Page mode cycle time for mixed (read and write) accesses.

tPC

× T

3.5 x Tc

40.0

35.0

—

132 CAS assertion to data valid (read)

tCAC

100 MHz:

× T

C − 7.0

—

13.0

133 Column address valid to data valid (read)

tAA

100 MHz:

× T

C − 7.0

—

23.0

134 CAS deassertion to data not valid (read hold time)

tOFF

0.0

—

135 Last CAS assertion to RAS deassertion

tRSH

2.5

× T

C − 4.0

21.0

—

136 Previous CAS deassertion to RAS deassertion

tRHCP

4.5

× T

C − 4.0

41.0

—

137 CAS assertion pulse width

tCAS

× T

C − 4.0

16.0

—

138 Last CAS deassertion to RAS assertion5

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

tCRP

2.25

× T

C − 6.0

3.75

× T

C − 6.0

4.75

× T

C − 6.0

6.75

× T

C − 6.0

—

41.5

61.5

—

Table 3-10

DRAM Page Mode Timings, Two Wait States1, 2, 3, 4 (continued)

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min

Max

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