DSP56362P datasheet(86/152 Pages) FREESCALE

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Serial Host Interface (SHI) I2C Protocol Timing

DSP56362 Technical Data, Rev. 4

3-60

Freescale Semiconductor

3.13.1

Programming the Serial Clock

The programmed serial clock cycle, TI

CCP, is specified by the value of the HDM[5:0] and HRS bits of

the HCKR (SHI clock control register).

The expression for TI

CCP is

where:

HRS is the prescaler rate select bit.

When HRS is cleared, the fixed divide-by-eight prescaler is operational.

When HRS is set, the prescaler is bypassed.

HDM[7:0] are the divider modulus select bits.

A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.

In I2C mode, the user may select a value for the programmed serial clock cycle from

The programmed serial clock cycle (TI2CCP), SCL rise time (TR), and the filters selected should be chosen

in order to achieve the desired SCL frequency, as shown in Table 3-23

187

Last SCL edge to HREQ output not

deasserted

Filters bypassed

Narrow filters enabled

Wide filters enabled

TAS;RQO

× T

C + 30

× T

C + 80

× T

C + 135

100

155

—

100

155

—

188

HREQ in assertion to first SCL edge

Filters bypassed

Narrow filters enabled

Wide filters enabled

TAS;RQI

0.5

× T

I2CCP

—

0.5

× T

C - 21

4327

4282

4238

—

927

882

838

—

Note: RP (min) = 1.5 k¾

Table 3-22 SHI I2C Protocol Timing (continued)

Standard I2C*

No.

Characteristics

Symbol/

Expression

Standard

Fast-Mode

Unit

Min

Max

Min

Max

2CCP

TC 2

HDM 7 0

[] 1

()

(

HRS

) 1

–

()

[]

6TC if HDM 5 0

[]

02 and HRS

()

4096 TC if HDM 7 0

[]

FF and HRS

()

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