IA186EM-PQF100I-R datasheet(44/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

POLLST (026h) – POLL STatus Register.

Master Mode

This register reflects the current state of the Poll register and can be read without affecting its contents.

However, when the Poll Register is read, it causes the current interrupt to be acknowledged and be

replaced by the next interrupt.

The poll status register is read-only.

IREQ

Reserved

S4 – S0

IREQ (bit 15) – Interrupt Request. This bit is set to 1 when an interrupt is pending. And during this

state, the S4 - S0 bits contain valid data.

Reserved (bits 14-6) Set to 0

S [4:0] (bit 4-0) – Poll Status. These bits show the interrupt type of the highest priority pending

interrupt.

The interrupt service routine does not begin execution automatically with the IS bit set. Rather, the

application software must execute the appropriate ISR.

POLL (024h) – POLL Register.

Master Mode

When the Poll Register is read, it causes the current interrupt to be acknowledged and be replaced by the

next interrupt. The poll status register reflects the current state of the Poll register and can be read without

affecting its contents.

The POLL register is read-only.

IREQ

Reserved

S4 – S0

IREQ (bit 15) – Interrupt Request. This bit is set to 1 when an interrupt is pending. And during this

state, the S4 - S0 bits contain valid data.

Reserved (bits 14-6)

S [4:0] (bit 4-0) – Poll Status. These bits show the interrupt type of the highest priority pending

interrupt.

EOI (022h) – End-Of-Interrupt Register.

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IA186EM-PQF100I-R 데이터시트(PDF) 44 Page - InnovASIC, Inc