IA186EM-PQF100I-R datasheet(15/133 Pages) INNOVASIC

15 / 133 page

IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

D0DSTL (0c4h)

The sixteen bits of these registers are combined with the four bits of the respective DMA Destination

Address High Register to produce a 20-bit destination address.

The D0DSTL and D1DSTL registers are undefined at reset.

7 6 5 4 3

DDA15 – DDA0

DDA [15:0] (bits 15-0) – DMA Destination Address Low bits are driven onto A15-A0 during the

write phase of a DMA transfer.

D1SRCH (0d2h) - DMA SouRCe Address High Register.

D0SRCH (0c2h)

The 20-bit source address consists of these four bits combined with the 16-bits of the respective Source

Address Low Register. A DMA transfer requires that two complete 16-bit registers in the peripheral

control block (high and low registers) be used for both the source and destination addresses of each DMA

channel involved. Each DMA channel requires that all four address registers be initialized. Each address

may be incremented or decremented independently of the other after each transfer. The addresses are

incremented or decremented by 2 for word transfers and incremented or decremented by 1 for byte

transfers.

The D0SRCH and D1SRCHL registers are undefined at reset.

7 6 5 4 3

Reserved

DSA19 –DSA16

Reserved [15:4] (bits 15-4) – Reserved

DSA [19:16] (bits 3-0) – DMA Source Address High bits are driven onto A19-A16 during the read

phase of a DMA transfer.

D1SRCL (0d0h) - DMA SouRCe Address Low Register.

D0SRCL (0c0h)

The sixteen bits of these registers are combined with the four bits of the respective DMA Source Address

High register to produce a 20-bit source address.

The D0SRCL and D1SRCL registers are undefined at reset.

7 6 5 4 3

DSA15-DSA0

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

IA186EM-PQF100I-R 데이터시트(PDF) 15 Page - InnovASIC, Inc