LTC2414IGN datasheet(12/48 Pages) LINER

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LTC2414/LTC2418

241418fa

first rising edge of SCK and depending on the control bits,

the converter updates its channel selection immediately

and is valid for the next conversion. The details of channel

selection control bits are described in the Input Data Mode

section. The output data is shifted out the SDO pin under

the control of the serial clock (SCK). The output data is

updated on the falling edge of SCK allowing the user to

reliably latch data on the rising edge of SCK (see Figure 3).

The data output state is concluded once 32 bits are read

out of the ADC or when CS is brought HIGH. The device

automatically initiates a new conversion and the cycle

repeats.

Through timing control of the CS and SCK pins, the

LTC2414/LTC2418 offer several flexible modes of opera-

tion (internal or external SCK and free-running conversion

modes). These various modes do not require program-

ming configuration registers; moreover, they do not dis-

turb the cyclic operation described above. These modes of

operation are described in detail in the Serial Interface

Timing Modes section.

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a Sinc or Comb filter). For

high resolution, low frequency applications, this filter is

typically designed to reject line frequencies of 50Hz or

APPLICATIO S I FOR ATIO

Figure 2. LTC2414/LTC2418 State Transition Diagram

CONVERT

POWER UP

IN+ = CH0, IN– = CH1

SLEEP

DATA OUTPUT

ADDRESS INPUT

241418 F02

TRUE

FALSE

CS = LOW

AND

SCK

60Hz plus their harmonics. The filter rejection perfor-

mance is directly related to the accuracy of the converter

system clock. The LTC2414/LTC2418 incorporate a highly

accurate on-chip oscillator. This eliminates the need for

external frequency setting components such as crystals or

oscillators. Clocked by the on-chip oscillator, the LTC2414/

LTC2418 achieve a minimum of 110dB rejection at the line

frequency (50Hz or 60Hz

±2%).

Ease of Use

The LTC2414/LTC2418 data output has no latency, filter

settling delay or redundant data associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog voltages is easy.

The LTC2414/LTC2418 perform offset and full-scale cali-

brations in every conversion cycle. This calibration is trans-

parent to the user and has no effect on the cyclic operation

described above. The advantage of continuous calibration

is extreme stability of offset and full-scale readings with re-

spect to time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2414/LTC2418 automatically enter an internal

reset state when the power supply voltage VCC drops

below approximately 2V. This feature guarantees the

integrity of the conversion result and of the serial interface

mode selection. (See the 3-wire I/O sections in the Serial

Interface Timing Modes section.)

When the VCC voltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)

signal with a typical duration of 1ms. The POR signal

clears all internal registers. Following the POR signal, the

LTC2414/LTC2418 start a normal conversion cycle and

follow the succession of states described above. The first

conversion result following POR is accurate within the

specifications of the device if the power supply voltage is

restored within the operating range (2.7V to 5.5V) before

the end of the POR time interval.

Reference Voltage Range

The LTC2414/LTC2418 accept a truly differential external

reference voltage. The absolute/common mode voltage

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