NAND512R3A2C datasheet(13/51 Pages) STMICROELECTRONICS

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NAND512-A2C

Signal descriptions

13/51

Signal descriptions

See Figure 1: Logic diagram, and Table 3: Signal names, for a brief overview of the signals

connected to this device.

3.1

Inputs/Outputs (I/O0-I/O7)

Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read

operation or input a command or data during a Write operation. The inputs are latched on

the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or

the outputs are disabled.

3.2

Inputs/Outputs (I/O8-I/O15)

Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data

during a Read operation or input data during a Write operation. Command and Address

Inputs only require I/O0 to I/O7.

The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when

the device is deselected or the outputs are disabled.

3.3

Address Latch Enable (AL)

The Address Latch Enable activates the latching of the Address inputs in the Command

Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.

3.4

Command Latch Enable (CL)

The Command Latch Enable activates the latching of the Command inputs in the Command

Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.

3.5

Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and read

circuitry. When Chip Enable is low, VIL, the device is selected.

If Chip Enable goes High (VIH) while the device is busy, the device remains selected and

does not go into standby mode.

3.6

Read Enable (R)

The Read Enable, R, controls the sequential data output during Read operations. Data is

valid tRLQV after the falling edge of R. The falling edge of R also increments the internal

column address counter by one.

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