NAND512R3A2C datasheet(16/51 Pages) STMICROELECTRONICS

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Bus operations

NAND512-A2C

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4.5

Write Protect

Write Protect bus operations are used to protect the memory against program or erase

operations. When the Write Protect signal is Low the device will not accept program or erase

operations and so the contents of the memory array cannot be altered. The Write Protect

signal is not latched by Write Enable to ensure protection even during power-up.

4.6

Standby

When Chip Enable is High the memory enters Standby mode, the device is deselected,

outputs are disabled and power consumption is reduced.

Table 5.

Bus operations

Bus Operation

I/O0 - I/O7

I/O8 - I/O15(1)

Only for x16 devices.

Command Input

VIL

VIH

Rising

X(2)

WP must be VIH when issuing a program or erase command.

Command

Address Input

VIL

VIH

VIL

VIH

Rising

Address

Data Input

VIL

VIH

Rising

Data Input

Data Output

VIL

Fallin

VIH

Data Output

Write Protect

VIL

Standby

VIH

XXXX

Table 6.

Address Insertion, x8 devices(1)(2)

A8 is set Low or High by the 00h or 01h Command, see Section 6.1: Pointer operations.

Any additional address input cycles will be ignored.

Bus

Cycle

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1st

2nd

A16

A15

A14

A13

A12

A11

A10

3rd

A24

A23

A22

A21

A20

A19

A18

A17

4th

VIL

A25

Table 7.

Address Insertion, x16 devices(1)(2)

A8 is Don’t Care in x16 devices.

Any additional address input cycles will be ignored.

Bus

Cycle

I/O8-

I/O15

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1st

2nd

A16

A15

A14

A13

A12

A11

A10

3rd

A24

A23

A22

A21

A20

A19

A18

A17

4th(4)

VIL

A25

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