| 전자부품 데이터시트 검색엔진 |
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PIC16F883-E/MLQTP 데이터시트(PDF) 86 Page - Microchip Technology |
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PIC16F883-E/MLQTP 데이터시트(HTML) 86 Page - Microchip Technology |
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86 / 288 page ![]() PIC16F882/883/884/886/887 DS41291D-page 84 Preliminary © 2007 Microchip Technology Inc. FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. C1POL C1OUT To PWM Logic RD_CM1CON0 Set C1IF To DQ EN Q1 Data Bus C1POL DQ EN CL Q3*RD_CM1CON0 Reset C1OUT (to SR Latch) MUX C1 0 1 2 3 C1ON(1) C1CH<1:0> 2 0 1 C1R MUX C1VIN- C1VIN+ C12IN0- C12IN1- C12IN2- C12IN3- C1IN+ + - 0 1 MUX CVREF C1RSEL FixedRef C1VREF MUX C2 C2POL C2OUT 0 1 2 3 C2ON(1) C2CH<1:0> 2 0 1 C2R From Timer1 Clock Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. MUX DQ EN DQ EN CL DQ RD_CM2CON0 Q3*RD_CM2CON0 Q1 Set C2IF To Reset C2VIN- C2VIN+ SYNCC2OUT C2IN+ C12IN0- C12IN1- C2IN2- C2IN3- 0 1 C2SYNC C2POL Data Bus MUX To Timer1 Gate, SR Latch 0 1 MUX CVREF C2RSEL FixedRef C2VREF and other peripherals |
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