HD64338024 datasheet(76/697 Pages) RENESAS

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Section 2 CPU

Rev. 7.00 Mar 10, 2005 page 34 of 652

REJ09B0042-0700

The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from

H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area

is also used as a vector area. See section 3.3, Interrupts, for details on the vector area.

If an odd address is specified as a branch destination or as the operand address of a MOV.W

instruction, the least significant bit is regarded as 0, causing word access to be performed at the

address preceding the specified address. See section 2.3.2, Memory Data Formats, for further

information.

2.4.2

Effective Address Calculation

Table 2.2 shows how effective addresses are calculated in each of the addressing modes.

Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,

CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).

Data transfer instructions can use all addressing modes except program-counter relative (7) and

memory indirect (8).

Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute

addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST

instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position

in the operand.

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