HD64338024 datasheet(18/697 Pages) RENESAS

18 / 697 page

Rev. 7.00 Mar 10, 2005 page xviii of xlii

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Page

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9.7.5 Application

Notes

328

Description amended

2. Use a clock with a frequency of up to 16 MHz for input to the

AEVH and AEVL pins, and ensure that the high and low widths

of the clock are at least half the OSC clock cycle duration. The

duty cycle is immaterial.

329

Description amended

Mode

Maximum AEVH/AEVL Pin Input

Clock Frequency

Watch, subactive, subsleep, standby

(

φw/2)

(

φw/4)

φw = 32.768 kHz or 38.4 kHz*

(

φw/8)

1000 kHz

500 kHz

250 kHz

Note:

* Does not apply to H8/38124 Group.

10.2.8 Bit Rate

Table 10.3 Examples

of BRR Settings for

Various Bit Rates

(Asynchronous

Mode) (2)

349

Table amended

10 MHz

Bit Rate

(bit/s)

Error

(%)

110

0.88

150

–1.36

200

1.73

250

–2.34

300

1.73

600

1.73

1200

1.73

2400

1.73

4800

1.73

9600

1.73

19200

1.73

31250

38400

1.73

Notes amended

1. The value set in BRR is given by the following equation:

N =

(32 • 2

2n • B)

– 1

where

B: Bit rate (bit/s)

N: Baud rate generator BRR setting (0

≤ N ≤ 255)

φ: System clock frequency

n: Baud rate generator input clock number (n = 0, 2, or 3)

(The relation between n and the clock is shown in table 10.4.)

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