HD64338024 datasheet(95/697 Pages) RENESAS

부품명	HD64338024

상세설명	Renesas 8-Bit Single-Chip Microcomputer Super Low Power Series

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제조업체	RENESAS [Renesas Technology Corp]

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Section 2 CPU

Rev. 7.00 Mar 10, 2005 page 53 of 652

REJ09B0042-0700

[Legend]

op:

rn:

IMM:

Operation field

Immediate data

RTE, SLEEP, NOP

LDC, STC (Rn)

IMM

ANDC, ORC,

XORC, LDC (#xx:8)

Figure 2.9 System Control Instruction Codes

2.5.8

Block Data Transfer Instruction

Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.

Table 2.11

Block Data Transfer Instruction

Instruction

Size

Function

EEPMOV

—

If R4L

≠ 0 then

repeat

@R5+

→ @R6+

R4L – 1

→ R4L

until

R4L = 0

else next;

Block transfer instruction. Transfers the number of data bytes

specified by R4L from locations starting at the address indicated by

R5 to locations starting at the address indicated by R6. After the

transfer, the next instruction is executed.

Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on

Use of the EEPMOV Instruction, for details.

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