HD64338024 datasheet(82/697 Pages) RENESAS

부품명	HD64338024

상세설명	Renesas 8-Bit Single-Chip Microcomputer Super Low Power Series

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Section 2 CPU

Rev. 7.00 Mar 10, 2005 page 40 of 652

REJ09B0042-0700

2.5.1

Data Transfer Instructions

Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats.

Table 2.4

Data Transfer Instructions

Instruction

Size*

Function

MOV

B/W

(EAs)

→ Rd, Rs → (EAd)

Moves data between two general registers or between a general

The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+

addressing modes are available for word data. The @aa:8

addressing mode is available for byte data only.

The @–R7 and @R7+ modes require word operands. Do not

specify byte size for these two modes.

POP

@SP+

→ Rn

Pops a 16-bit general register from the stack. Equivalent to

MOV.W @SP+, Rn.

PUSH

→ @–SP

Pushes a 16-bit general register onto the stack. Equivalent to

MOV.W Rn, @–SP.

Notes: *

Size: Operand size

Byte

Word

Certain precautions are required in data access. See section 2.9.1, Notes on Data Access, for

details.

Figure 2.7 lists the format of the bit manipulation instructions.

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