| 전자부품 데이터시트 검색엔진 |
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CS42428 데이터시트(PDF) 13 Page - Cirrus Logic |
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CS42428 데이터시트(HTML) 13 Page - Cirrus Logic |
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13 / 73 page ![]() DS605F1 13 CS42428 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CL =30 pF) Notes: 20. Data must be held for sufficient time to bridge the transition time of CCLK. 21. For fsck <1 MHz. Parameter Symbol Min Typ Max Units CCLK Clock Frequency fsck 0- 6.0 MHz CS High Time Between Transmissions tcsh 1.0 - - µs CS Falling to CCLK Edge tcss 20 - - ns CCLK Low Time tscl 66 - - ns CCLK High Time tsch 66 - - ns CDIN to CCLK Rising Setup Time tdsu 40 - - ns CCLK Rising to DATA Hold Time (Note 20) tdh 15 - - ns CCLK Falling to CDOUT Stable tpd -- 50 ns Rise Time of CDOUT tr1 -- 25 ns Fall Time of CDOUT tf1 -- 25 ns Rise Time of CCLK and CDIN (Note 21) tr2 -- 100 ns Fall Time of CCLK and CDIN (Note 21) tf2 -- 100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh Figure 4. Control Port Timing - SPI Format |
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