CS42428 datasheet(38/73 Pages) CIRRUS

38 / 73 page

DS605F1

CS42428

4.9

Power Supply, Grounding, and PCB Layout

As with any high-resolution converter, the CS42428 requires careful attention to power supply and ground-

ing arrangements if its potential performance is to be realized. Figure 5 and 6 show the recommended power

arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from

the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this

case, no additional devices should be powered from VD.

For applications where the output of the PLL is required to be low jitter, use a separate, low-noise analog

+5 V supply for VA, decoupled to AGND. In addition, a separate region of analog ground plane around the

FILT+, VQ, LPFLT, REFGND, AGND, and VA pins is recommended.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling

capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42428 as pos-

sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same

side of the board as the CS42428 to minimize inductance effects. All signals, especially clocks, should be

kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and

PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the

electrical path from FILT+ and REFGND. The CDB42428 evaluation board demonstrates the optimum lay-

out and power supply arrangements.

CS42428 데이터시트(PDF) 38 Page - Cirrus Logic