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CS42428 데이터시트(PDF) 29 Page - Cirrus Logic |
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CS42428 데이터시트(HTML) 29 Page - Cirrus Logic |
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29 / 73 page ![]() DS605F1 29 CS42428 D AC_LRCK ADC_LRCK DAC_SCLK ADC_SCLK LS B MSB 20 clks 64 clks 64 clks LS B MSB LS B MSB LS B MSB LS B MSB LS B MSB MS B DAC1 DA C3 D AC5 D AC2 DAC4 DAC6 20 clks 20 clks 20 clks 20 clks 20 clks Left Channel Right C hannel 20 clks DAC 7 DAC8 20 clks DAC_SDIN 4 20 clks ADC 1 A DC3 A DC5 ADC2 ADC4 ADC6 20 clks 20 clks 20 clks 20 clks 20 clks ADC_SDO UT DAC_SDIN 1 Figure 14. One Line Mode #1 Serial Audio Format One Line Data Mode #1, Data Valid on Rising Edge of SCLK Bits/Sample SCLK Rate(s) Notes Master Slave 20 128 Fs 128 Fs single-speed mode 128 Fs 128Fs double-speed mode LS B MSB 24 clks 128 clks LS B MSB LS B MSB LS B MSB LS B MSB LS B MSB MSB DAC1 DAC3 D AC5 D AC2 D AC4 D AC6 24 clks 24 clks 24 clks 24 clks 24 clks Left Channel Right C hannel 24 clks DAC 7 DAC8 24 clks 24 clks ADC 1 A DC3 A DC5 ADC2 ADC4 ADC6 24 clks 24 clks 24 clks 24 clks 24 clks 128 clks D AC_LRCK A DC_LRCK DAC_SCLK A DC_SCLK ADC_SDO UT DAC_SDIN1 DAC_SDIN4 Figure 15. One Line Mode #2 Serial Audio Format One Line Data Mode #2, Data Valid on Rising Edge of SCLK Bits/Sample SCLK Rate(s) Notes Master Slave 24 256 Fs not supported single-speed mode |
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