PM5366-PI datasheet(117/267 Pages) PMC

117 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

105

optionally asserted and the Elastic Store read and write address are reset to the

startup values (logically 180 degrees apart).

9.27.3 DS3 Desynchronizer

The Desynchronizer monitors the Elastic Store level to control the de-stuffing

algorithm to avoid overflow and underflow conditions. The Desynchronizer

assumes either a 51.84 MHz clock or a 44.928 MHz clock (provided via input

CLK52M).

When using a 44.928 MHz CLK52M clock, the DS3 clock is generated using a

fixed 8 KHz interval. The 8KHz interval is subdivided into 9 rows. Each row

contains either 621 or 622 clock periods. The CLK52M contains 624 cycles per

row. To generate 621 pulses, a gap pattern of 207 clocks + 1 clock gap + 207

clocks + 1 clock gap + 207 clocks + 1 clock gap is used. To generate 622

pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap +

208 clocks is used.

When using a 51.84 MHz CLK52M clock, the DS3 clock is generated using

similar gapping patterns. To generate 621 pulses per row, a gapping pattern of

63 * (7 clocks + 1 clock gap) + 36 * (5 clocks + 1 clock gap) is used. To generate

622 pulses per row, a gapping pattern of 63 * (7 clocks + 1 clock gap) + 35 * (5

clocks + 1 clock gap) + 6 clocks) is used.

Table 7 illustrates the gap patterns used to generate the desynchronized DS3

clock under the normal, DS3 AIS, faster and slower status. The faster pattern is

used to drain the elastic store to avoid overflows. The slower pattern is used to

allow the elastic store to fill to avoid underflows.

PM5366-PI 데이터시트(PDF) 117 Page - PMC-Sierra, Inc