PM5366-PI datasheet(121/267 Pages) PMC

121 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

109

The Tributary Mapper may optionally act as a time switch. When Time Switch

Enable is active, the association of Tributary Mapper VT Payloads to logical FIFO

data streams is software configurable. There are two pages in the time switch

configuration RAM. One page is software selectable to be the active page and

the other the stand-by page. The configuration in the active page is used to

associate outgoing VT Payloads to logical FIFOs. The stand-by page can be

programmed to the next switch configuration. Change of page selection is

synchronized to incoming stream frame boundaries. When Time Switch Enable

is inactive, the association of outgoing VT Payloads to logical FIFOs is fixed.

The TTMP outputs the STS-1, TUG3 in a STM-1/VC4 or STM-1/VC3 with the bit

asynchronous mapped T1s or E1s onto an internal bus for further processing by

the Transmit Tributary Payload Processor block.

9.31 Transmit Tributary Byte Synchronous Mapper

Each one of three Transmit Tributary Mapper blocks byte synchronously maps

up to 28 T1 or 21 E1 streams into an STS-1 SPE, TUG3 in a STM-1/VC4 or

STM-1/VC3 payload. The mapping is done inaccordance with ITU-T

Recommendation G.709 and ANSI T1.105.

Byte synchronous mapping is enabled on a per-tributary basis by setting the

ENBL bit through the Byte Synchronous Mapping Tributary Control RAM Indirect

Access Data register, by bypassing the transmit jitter attenuator by setting the

TJATBYP bit through theTJAT Indirect Channel Data register and by disabling

the egress VTPP pointer interpretation via the EPTRBYP or ETVTPTRDIS bits.

By default the T1/E1 framer inserts valid framing into the T1 ‘F’ bit and E1 TS0.

The T1 signaling received from the system interface is encoded into the

S1S2S3S4 bit positions. Signaling is also inserted into the robbed bit signaling

positions as enabled by the SIGC bits programmed through the TPCC Indirect

Channel Data registers. For E1, the signaling insertion is independent of the

mapping.

9.32 DS3 Mapper ADD Side (D3MA)

Each one of three DS3 Mapper ADD Side (D3MA) blocks maps a DS3 signal into

an STS-1 (STM-0/AU3) payload and compensate for any frequency differences

between the incoming DS3 serial bit rate (TICLK) and the available STS-1

(STM-0/AU3) SPE mapped payload capacity. The asynchronous DS3 mapping

consists of 9 rows every 125 µs (8 KHz). Each row contains 621 information bits,

5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication

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