PM7344 datasheet(55/293 Pages) PMC

55 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

The interrupt is cleared at the start of the next RFDL Data Register read that

results in an empty FIFO buffer. This is independent of the FIFO buffer fill

level for which the interrupt is programmed. If there is still data remaining in

the buffer, RDLINT will remain high. An interrupt due to a RFDL FIFO buffer

overrun condition is not cleared on a RFDL Data Register read but on a

RFDL Status Register read. The RDLINT output can always be forced low by

disabling the RFDL (setting the EN bit in the RFDL Configuration Register to

logic 0, or by disabling the internal HDLC receiver in the S/UNI-MPH Receive

Data Link Configuration Register), or by forcing the RFDL to terminate

reception (setting the TR bit in the RFDL Configuration Register to logic 1).

The RDLINT output may be forced low by disabling the interrupts with the

RFDL Interrupt Status/Control Register. However, the internal interrupt latch

is not cleared, and the state of this latch can still be read through the RFDL

Interrupt Status/Control Register.

7. The RDLEOM[x] output goes high:

1) immediately on detection of RFDL FIFO buffer overrun,

2) when the data byte written into the RFDL FIFO buffer due to an end of

message condition is read,

3) when the data byte written into the RFDL FIFO buffer due to an abort

condition is read, or,

4) when the data byte written into the RFDL FIFO buffer due to the transition

from receiving all ones to flags is read.

RDLEOM[x] is set low by reading the RFDL Status Register or by disabling

the RFDL.

8. For each TDLUDR[x] output:

The TDLUDR[x] output goes high when the processor is unable to service the

TDLINT[x] request for more data before a specific time-out period. This

period is dependent upon the frequency of TDLCLK:

1) for a TDLCLK frequency of 4 kHz (ESF FDL at the full 4 kHz rate), the

time-out is 1.0 ms;

2) for a TDLCLK frequency of 2 kHz (half the ESF FDL), the time-out is 2.0

ms;

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