| 전자부품 데이터시트 검색엔진 |
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PM7344 데이터시트(PDF) 68 Page - PMC-Sierra, Inc |
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PM7344 데이터시트(HTML) 68 Page - PMC-Sierra, Inc |
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68 / 293 page ![]() PM7344 S/UNI-MPH DATA SHEET PMC-950449 ISSUE 6 MULTI-PHY USER NETWORK INTERFACE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 52 Figure 10 - E1 Jitter Tolerance 100 10 1.0 0.1 1 10 100 1k 10k Jitter Frequency, Hz Jitter Amplitude, UI pp 0.01 100k 35 acceptable ITU G.823 unacceptable Region 0.2 DJAT minimum tolerance 1.5 20 2.4 k 1 8k 40 The accuracy of the XCLK frequency and that of the DJAT PLL reference input clock used to generate the jitter-free TCLKO have an effect on the minimum jitter tolerance. For T1 interfaces, the DJAT PLL reference clock accuracy can be ±200 Hz from 1.544 MHz, and the XCLK input accuracy can be ±100 ppm from 37.056 MHz. For E1 interfaces, the PLL reference clock accuracy can be ± 103 Hz from 2.048 MHz, and the XCLK input accuracy can be ±100 ppm from 49.152 MHz. The minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK/24 are shown in Figure 11 and Figure 12. |
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