PM7366-PI datasheet(108/286 Pages) PMC

108 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

Unused

Bit 14

R/W

TP2EN

Bit 13

R/W

TABRT2EN

Bit 12

R/W

RP2EN

Bit 11

R/W

RLENE2EN

Bit 10

R/W

RABRT2EN

Bit 9

R/W

RFCSE2EN

Bit 8

R/W

RSPE2EN

Bit 7

Unused

Bit 6

R/W

TP1EN

Bit 5

R/W

TABRT1EN

Bit 4

R/W

RP1EN

Bit 3

R/W

RLENE1EN

Bit 2

R/W

RABRT1EN

Bit 1

R/W

RFCSE1EN

Bit 0

R/W

RSPE1EN

This register configures the events that are accumulated in the two configurable performance

monitor counters in the PMON block.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

RSPE1EN:

The receive small packet error accumulate enable bit (RSPE1EN) enables counting of

minimum packet size violation events. When RSPE1EN is set high, receipt of a packet that is

shorter than 32 bits (CRC-CCITT, Unspecified CRC or no CRC) or 48 bits (CRC-32) will

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