PM7367 datasheet(23/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

PIN DESCRIPTION

Table 1 – Line Side Interface Signals (132)

Pin Name

Type

No.

Function

RCLK[0]

RCLK[1]

RCLK[2]

RCLK[3]

RCLK[4]

RCLK[5]

RCLK[6]

RCLK[7]

RCLK[8]

RCLK[9]

RCLK[10]

RCLK[11]

RCLK[12]

RCLK[13]

RCLK[14]

RCLK[15]

RCLK[16]

RCLK[17]

RCLK[18]

RCLK[19]

RCLK[20]

RCLK[21]

RCLK[22]

RCLK[23]

RCLK[24]

RCLK[25]

RCLK[26]

RCLK[27]

RCLK[28]

RCLK[29]

RCLK[30]

RCLK[31]

Input

C10

A10

C11

A12

C12

A13

C13

B14

A15

D14

A16

C16

D16

W17

Y17

The receive line clock signals (RCLK[31:0])

contain the recovered line clock for the 32

independently timed links. Processing of

the receive links is on a priority basis, in

descending order from RCLK[0] to

RCLK[31]. Therefore, the highest rate link

should be connected to RCLK[0] and the

lowest to RCLK[31]. RD[31:0] is sampled

on the rising edge of the corresponding

RCLK[31:0] clock.

For channelised T1 or E1 links, RCLK[n]

must be gapped during the framing bit (for

T1 interfaces) or during time-slot 0 (for E1

interfaces) of the RD[n] stream. The

FREEDM-32P32 uses the gapping

information to determine the time-slot

alignment in the receive stream.

RCLK[31:0] is nominally a 50% duty cycle

clock of 1.544 MHz for T1 links and 2.048

MHz for E1 links.

For unchannelised links, RCLK[n] must be

externally gapped during the bits or time-

slots that are not part of the transmission

format payload (i.e. not part of the HDLC

packet). RCLK[2:0] is nominally a 50% duty

cycle clock between 0 and 52 MHz.

RCLK[31:3] is nominally a 50% duty cycle

clock between 0 and 10 MHz.

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