PM7367 datasheet(124/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

110

TSLOT[4:0]:

The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be

configured or interrogated in the indirect access. For a channelised T1 link,

time-slots 1 to 24 are valid. For a channelised E1 link, time-slots 1 to 31 are

valid. For unchannelised links, only time-slot 0 is valid.

LINK[4:0]:

The indirect link number bits (LINK[4:0]) select amongst the 32 receive links

to be configured or interrogated in the indirect access.

RWB:

The indirect access control bit (RWB) selects between a configure (write) or

interrogate (read) access to the channel provision RAM. The address to the

channel provision RAM is constructed by concatenating the TSLOT[4:0] and

LINK[4:0] bits. Writing a logic zero to RWB triggers an indirect write

operation. Data to be written is taken from the PROV, the CDLBEN and the

CHAN[4:0] bits of the RCAS Indirect Channel Data register. Writing a logic

one to RWB triggers an indirect read operation. Addressing of the RAM is the

same as in an indirect write operation. The data read can be found in the

PROV, the CDLBEN and the CHAN[4:0] bits of the RCAS Indirect Channel

Data register.

BUSY:

The indirect access status bit (BUSY) reports the progress of an indirect

access. BUSY is set high when this register is written to trigger an indirect

access, and will stay high until the access is complete. At which point, BUSY

will be set low. This register should be polled to determine when data from an

indirect read operation is available in the RCAS Indirect Channel Data

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