PM7367 datasheet(191/323 Pages) PMC

191 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

177

memory. When ENABLE is set high, the TMAC is enabled. When ENABLE

is set low, the TDR Ready Queue is ignored. Once all linked lists of TDs built

up by the TMAC have been exhausted, no more data will be transmitted on

the TD[31:0] links.

CACHE:

The transmit descriptor reference cache enable bit (CACHE) controls the

frequency at which TDRs are written to the TDR Free Queue. When CACHE

is set high, freed TDRs are cache and then written up to six at a time. When

CACHE is set low, freed TDRs are written one at a time.

TDQ_RDYN[2:0]:

The TDQ_RDYN[2:0] field sets the number of transmit descriptor references

(TDRs) that must be read from the TDR Ready Queue before the TDR Ready

interrupt (TDQRDYI) is asserted, as follows:

Table 20 – TDQ_RDYN[2:0] Settings

TDQ_RDYN[2:0]

No of TDRs

000

001

010

011

100

101

110

Reserved

111

Reserved

TDQ_FRN[1:0]:

The TDQ_FRN[1:0] field sets the number of times that a block of TDRs are

written to the TDR Free Queue from the TMACs internal cache before the

TDR Free Queue Interrupt (TDQFI) is asserted, as follows:

Table 21 – TDQ_FRN[1:0] Settings

TDQ_FRN[1:0]

No of Reads

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