7/29

STW81100

≤ 10 MHz are allowed)

2. see relationship between ICP and REXT in the Circuit Description section (Charge Pump)

3. PFD frequency leakage (400KHz) and harmonics

4. Guaranteed by design and characterization.

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

Current Consumption

DIV4 Buff

26

mA

DIV2 Buff

23

mA

Direct Output

37

mA

EXTERNAL VCO (Test purpose only)

Frequency range

3.3

4.4

GHz

Input level

0

+6

dBm

DC Input level

2

V

Current Consumption

VCO Internal Buffer

15

mA

PLL MISCELLANEOUS

Current Consumption

Input Buffer, Prescaler, Digital

Dividers, misc

10

mA

40 KHz PLL bandwidth; within

1 ppm of frequency error

150

µs

Parameter

Test Condition

Min

Typ

Max

Units

Normalized In Band Phase Noise

Floor

ICP= 2mA, PLL BW = 50KHz;

including reference clock contribution

-212

dBc/Hz

In Band Phase Noise Floor

Direct Output

In Band Phase Noise Floor

Divider by 2

In Band Phase Noise Floor

Divider by 4

PLL Integrated Phase Noise with Divider by 2

Integrated Phase Noise (single

sided) 400Hz to 4MHz

(N = 10000), PLL BW = 15KHz

-39

-37

dBc

Integrated Phase Noise (single

sided) 100Hz to 25MHz

-38

-36

dBc

VCO A Direct (3300MHz-3900MHz) – Open Loop

Phase Noise @ 1 KHz

-56

-53

dBc/Hz

Phase Noise @ 10 KHz

-83

-82

dBc/Hz

Phase Noise @ 100 KHz

-105

-102

dBc/Hz

Phase Noise @ 1 MHz

-128

-125

dBc/Hz

Phase Noise @ 10 MHz

-148

-145

dBc/Hz

Phase Noise @ 40 MHz

-156

-153

dBc/Hz

Table 6. Electrical Characteristcs (continued)