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STW81100

7.6 Lock Detect

This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found

to be shorter than the fixed delay (roughly 5 ns). Lock Detect signal is high when the PLL is locked.

When Power Down is activated, Lock Detect is let to high level (Lock Detect consumes current only during

PLL transients).

7.7 Charge Pump

This block drives two matched current sources, Iup and Idown, which are controlled respectively by UP

and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to

be connected to the REXT input pin) and a selection among 8 by a 3 bit word.

Table 8. Current Value vs Selection

Note: The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are forced to VDD/2.

Figure 15. Loop Filter Connection

CPSEL2

CPSEL1

CPSEL0

Current

Value for REXT=9.1 K

Ω

00

0

0.25 mA

00

1

0.50 mA

01

0

0.75 mA

01

1

1.00 mA

10

0

1.25 mA

10

1

1.50 mA

11

0

1.75 mA

11

1

2.00 mA

Charge

Pump

ICP

VCTRL

BUF

VDD

BUF

Cal bit

R1

C1

C3

R3

C2

C3

R3

C2