TMP91CW60DFG datasheet(21/262 Pages) TOSHIBA

21 / 262 page

Page 18

2007-12-03

TMP91CW60

Example 3:

X:Don’t care

(Clock gear changing)

To change the clock gear, write the register value to the SYSCR1<GEAR2:0> register. It is necessary the

warm-up time until changing after writing the register value.

There is the possibility that the instruction next to the clock gear changing instruction is executed by the

clock gear before changing. To execute the instruction next to the clock gear switching instruction by the clock

gear after changing, input the dummy instruction as follows (instruction to execute the write cycle).

(3)Internal clock output

The fSYS or fs internal clock can be driven out from the P40/SCOUT pin.

The P40/SCOUT pin is configured as SCOUT (System clock output) by programming the port 4 regis-

ters as follows: P4CR<P40C> = "1" and P4FC<P40F> = "1". The output clock is selected through the

SYSCR2<SCOSEL> bit.

Table 2-3 shows the pin states in each clocking mode when the P40/SCOUT pin is configured as

SCOUT.

2.3.4

Prescaler Clock Controller

For the internal I/O (TMRA01 to TMRA45, TMRB0 to TMRB4, SIO0 to SIO2, SBI0, SBI1) there is a pres-

caler which can divide the clock.

The φT0 clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 4.

The setting of the SYSCR0<PRCK1> register determines which clock signal is input.

Changing to a clock gear

SYSCR1

EQU

00E1H

(SYSCR1),XXXX0000B

;

Changes fSYS to fc/2.

SYSCR1

EQU

00E1H

(SYSCR1),XXXX0000B

;

Changes fSYS to fc/2.

(DUMMY),00H

;

Dummy instruction

Instruction to be executed after clock gear has changed.

Table 2-3

SCOUT Output States

NORMAL SLOW

HALT mode

IDLE2

IDLE1

STOP

<SCOSEL>="0"

The fs clock is driven out.

HOLD at either "1"

or "0"

<SCOSEL>="1"

The f

SYS clock is driven out.

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