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TMP86FS23UG 데이터시트(PDF) 70 Page - Toshiba Semiconductor |
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TMP86FS23UG 데이터시트(HTML) 70 Page - Toshiba Semiconductor |
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70 / 252 page ![]() Page 58 5. I/O Ports 5.4 Port P5 (P57 to P50) TMP86FS23UG Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. P5DR (0005H) R/W 76 543 21 0 P57 SEG16 P56 SEG17 P55 SEG18 P54 SEG19 P53 SEG20 P52 SEG21 P51 SEG22 P50 SEG23 (Initial value: 0000 0000) P5LCR (0F9FH) 76 543 21 0 (Initial value: 0000 0000) P5LCR Port P5/segment output control (Set for each bit individually) 0: P5 input/output port 1: LCD segment output R/W P5CR (000AH) 76 543 21 0 (Initial value: 0000 0000) P5CR P5 port input/output control (Set for each bit individually) 0: Input mode 1: Output mode R/W |
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