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TMP86FS23UG 데이터시트(PDF) 95 Page - Toshiba Semiconductor |
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TMP86FS23UG 데이터시트(HTML) 95 Page - Toshiba Semiconductor |
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95 / 252 page ![]() Page 83 TMP86FS23UG 8.3 Function TC1 has four operating modes. The timer mode of the TC1 is used at warm-up when switching form SLOW mode to NORMAL2 mode. 8.3.1 Timer mode In this mode, counting up is performed using the internal clock. The contents of TREGIA are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. Counting up resumes after the counter is cleared. Note: When fc is selected for the source clock in SLOW mode, the lower bits 11 of TREG1A is invalid, and a match of the upper bits 7 makes interrupts. TC1 status register TC1SR (0016H) 7 6 54 3210 HECF HEOVF "0" "0" "0" "0" "0" "0" (Initial value: 0000 0000) HECF Operating Status monitor 0: 1: Stop (during Tb) or disable Under counting (during Ta) Read only HEOVF Counter overflow monitor 0: 1: No overflow Overflow status Table 8-1 Source clock (internal clock) of Timer/Counter 1 Source Clock Resolution Maximum Time Setting NORMAL1/2, IDLE1/2 Mode SLOW Mode SLEEP Mode fc = 16 MHz fs =32.768 kHz fc = 16 MHz fs =32.768 kHz DV7CK = 0 DV7CK = 1 fc/223 [Hz] fs/215 [Hz] fs/215 [Hz] fs/215 [Hz] 0.52 s 1 s 38.2 h 72.8 h fc/213 fs/25 fs/25 fs/25 512 ms 0.98 ms 2.2 min 4.3 min fc/211 fs/23 fs/23 fs/23 128 ms 244 ms 0.6 min 1.07 min fc/27 fc/27 -- 8 ms - 2.1 s - fc/23 fc/23 - - 0.5 ms - 131.1 ms - fc fc fc (Note) - 62.5 ns - 16.4 ms - fs fs - - - 30.5 ms - 8 s |
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