M58BW016DB datasheet(20/69 Pages) STMICROELECTRONICS

20 / 69 page

Bus operations

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

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3.1.7

Standby mode

When Chip Enable is High, VIH, and the Program/Erase controller is idle, the memory enters

Standby mode, the power consumption is reduced to the standby level and the Data

inputs/outputs pins are placed in the high impedance state regardless of Output Enable,

Write Enable or Output Disable inputs.

3.1.8

Automatic Low Power mode

If there is no change in the state of the bus for a short period of time during Asynchronous

Bus Read operations the memory enters Auto Low Power mode where the internal Supply

current is reduced to the Auto-Standby Supply current. The Data inputs/outputs will still

output data if a Bus Read operation is in progress.

Automatic Low Power is only available in Asynchronous Read modes.

3.1.9

Power-down mode

The memory is in Power-down when Reset/Power-down, RP, is at VIL. The power

consumption is reduced to the power-down level and the outputs are high impedance,

independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable,

W, inputs.

3.1.10

Electronic signature

Two codes identifying the manufacturer and the device can be read from the memory

allowing programming equipment or applications to automatically match their interface to

the characteristics of the memory. The electronic signature is output by giving the Read

Electronic Signature command. The manufacturer code is output when all the address

inputs are at VIL. The device code is output when A1 is at VIH and all the other address pins

are at VIL (see Table 5: Asynchronous Read Electronic Signature operation). Issue a Read

Memory Array command to return to Read mode.

Table 4.

Asynchronous Bus operations(1)

X = Don’t care.

Bus Operation

Step

A0-A18

DQ0-DQ31

Asynchronous Bus Read

VIL VIL VIH VIH VIH

VIL

Address

Data output

Asynchronous Latch

Controlled Bus Read

Address Latch

VIL VIH VIH

VIL

VIH

VIL

Address

High-Z

Read

VIL VIL VIH VIH VIH VIH

Data output

Asynchronous Page

Read

VIL VIL VIH VIH VIH

Address

Data output

Asynchronous Bus Write

VIL VIH

XVIL

VIH

VIL

Address

Data input

Asynchronous Latch

Controlled Bus Write

Address Latch

VIL VIL VIH VIH VIH

VIL

Address

High-Z

Write

VIL VIH

XVIL

VIH VIH

Data input

Output Disable, G

VIL VIH VIH VIH VIH

High-Z

Output Disable, GD

VIL VIL

VIL

VIH VIH

High-Z

Standby

VIH

High-Z

Reset/Power-down

VIL

High-Z

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