ST10F271B datasheet(173/180 Pages) STMICROELECTRONICS

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ST10F271B/ST10F271E

Electrical characteristics

173/180

24.8.20

High-speed synchronous serial interface (SSC) timing

Master mode

VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

Table 81.

SSC master mode timings

Symbol

Parameter

Max. Baudrate 6.6MBd

(1)@F

CPU = 40MHz

(<SSCBR> = 0002h)

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

min.

max.

min.

max.

t300

CC SSC clock cycle time(2))

150

8TCL

262144 TCL

t301

CC SSC clock high time

–

t300 / 2 – 12

–

t302

CC SSC clock low time

–

t300 / 2 – 12

–

t303

CC SSC clock rise time

–

t304

CC SSC clock fall time

–

t305

CC Write data valid after shift edge

–

t306

CC Write data hold after shift edge(3)

– 2

–

– 2

–

t307p

Read data setup time before latch

edge, phase error detection on

(SSCPEN = 1)

37.5

–

2TCL + 12.5

–

t308p

Read data hold time after latch

edge, phase error detection on

(SSCPEN = 1)

–

4TCL

–

t307

Read data setup time before latch

edge, phase error detection off

(SSCPEN = 0)

–2TCL–

t308

Read data hold time after latch

edge, phase error detection off

(SSCPEN = 0)

0–0

–

Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with

48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher

than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only

with CPU clock equal to (or lower than) 32MHz.

Formula for SSC Clock Cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC

Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125ns (corresponding to 8Mbaud).

Partially tested, guaranteed by design characterization.

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