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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8994ECS/R 데이터시트(PDF) 38 Page - Cirrus Logic |
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WM8994ECS/R 데이터시트(HTML) 38 Page - Cirrus Logic |
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38 / 363 page  WM8994 38 Rev 4.6 DIGITAL AUDIO INTERFACE - TDM MODE When TDM operation is used on the ADCDATn pins, it is important that two devices do not attempt to drive the ADCDATn pin simultaneously. To support this requirement, the ADCDATn pins can be configured to be tri-stated when not outputting data. The timing of the WM8994 ADCDATn tri-stating at the start and end of the data transmission is described in Figure 6 below. BCLK ADCDAT ADCDAT set-up time ADCDAT release time ADCDAT undriven (tri-state) ADCDAT valid (CODEC output) ADCDAT valid ADCDAT undriven (tri-state) Figure 6 Audio Interface Timing - TDM Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER MIN TYP MAX UNIT TDM Timing - Master Mode ADCDAT setup time from BCLK falling edge 0 ns ADCDAT release time from BCLK falling edge 15 ns TDM Timing - Slave Mode ADCDAT setup time from BCLK falling edge 5 ns ADCDAT release time from BCLK falling edge 32 ns |
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